A WiMAX turbo decoder with tailbiting BIP architecture

Author

Arai, Hiroaki ; Miyamoto, Naoto ; Kotani, Koji ; Fujisawa, Hisanori ; Ito, Takashi

Author_Institution

Grad. Sch. of Electron. Eng., Tohoku Univ., Sendai, Japan

fYear

2010

Firstpage

371

Lastpage

372

Abstract

A tailbiting block-interleaved pipelining (TB-BIP) is proposed for deeply-pipelined turbo decoders. Conventional sliding window block-interleaved pipelining (SW-BIP) turbo decoders suffer from many warm-up calculations when the number of pipeline stages is increased. However, by using TB-BIP, more than 50% of the warm-up calculations are reduced as compared to SW-BIP. We have implemented a TB-BIP WiMAX turbo decoder with four pipeline stages in the area of 3.8 mm² using a 0.18 Â¿m CMOS technology. The chip achieved 45 Mbps/iter and 3.11 nJ/b/iter at 99 MHz operation.

Keywords

CMOS integrated circuits; WiMax; block codes; interleaved codes; pipeline processing; turbo codes; CMOS technology; TB-BIP WiMAX turbo decoder; deeply-pipelined turbo decoder; frequency 99 MHz; size 0.18 mum; sliding window block-interleaved pipelining; tailbiting BIP architecture; tailbiting block-interleaved pipelining; warm-up calculation; Bit error rate; CMOS technology; Decoding; Electronics industry; Indium tin oxide; Industrial electronics; Laboratories; Pipeline processing; Turbo codes; WiMAX;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific

Conference_Location

Taipei

Print_ISBN

978-1-4244-5765-6

Electronic_ISBN

978-1-4244-5767-0

Type

conf

DOI

10.1109/ASPDAC.2010.5419858

Filename

5419858