Run-time generation of partial configurations for arithmetic expressions

Adaptive embedded systems can achieve enhanced flexibility by performing run-time reconfiguration of hardware. This paper describes a method to generate at run-time new partial FPGA configurations corresponding to arithmetic expressions. This is achieved by merging available partial bitstreams of arithmetic components to produce a new partial bitstream for a specific FPGA area. The connections among the components are mapped to the switch matrices of the reconfigurable fabric, and the corresponding information is added to the new partial configuration. The proposed method was implemented for a Virtex-II Pro FPGA with a 300 MHz PowerPC 405 CPU. It was used to create partial configurations in less than 69 s for sets of arithmetic circuits with up to 25 components and 208 connections.