Probabilistic resource estimation for pipeline architecture

This paper presents a new approach to resource estimation in high level synthesis. Given a set of operators and a data flow graph specification, we apply a probability based method to compute the probable numbers of operators, registers, bus and operator connections for each time step or algorithm latency. Combined with statistical metrics, we obtain a quick and accurate estimation module that includes real precedence constraints. The aim of this work is to provide ASICs designers with a guidance tool for a better use of high level synthesis. Algorithm properties like dated resource concurrence and operator link statistics are computed to guide algorithmic, transformations and hardware selection