Title :
Cascaded time difference amplifier using differential logic delay cell
Author :
Mandai, Shingo ; Nakura, Toru ; Ikeda, Makoto ; Asada, Kunihiro
Author_Institution :
Dept. of Electr. Eng. & Inf. Syst., Univ. of Tokyo, Tokyo, Japan
Abstract :
We introduce a 42x cascaded time difference amplifier (TDA) using differencial logic delay cells with 0.18¿m CMOS process. By employing differential logic cells for the delay chain instead of CMOS logic cells, our TDA has stable time difference gain (TD gain) and fine time resolution. Measurement results show that our TDA achieves less than 5.5% TD gain offset and ±250ps input range.
Keywords :
CMOS logic circuits; amplifiers; CMOS logic cells; CMOS process; cascaded time difference amplifier; differential logic delay cell; fine time resolution; size 0.18 mum; time difference gain; CMOS logic circuits; CMOS process; Delay effects; Differential amplifiers; Gain control; Gain measurement; Power supplies; Semiconductor device measurement; Switches; Switching circuits;
Conference_Titel :
Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-5765-6
Electronic_ISBN :
978-1-4244-5767-0
DOI :
10.1109/ASPDAC.2010.5419866
