Title :
A low-voltage, low-power, high-linearity cmos four-quadrant analog multiplier
Author :
Sawigun, Chutham ; Demosthenous, Andreas ; Pal, Dipankar
Author_Institution :
Dept. of Electron. Eng., Mahanakorn Univ. of Technol., Bangkok
Abstract :
A compact four-quadrant analog multiplier circuit using strong inversion saturated MOSFETs is presented. The circuit is formed by connecting simple 2-input "combiner" and "subtracter" cells in a novel topology. The proposed multiplier features low-voltage operation, very low quiescent power consumption, high-linearity and high operating frequency. In comparison with a previously reported multiplier circuit, simulated results using a 0.35-mum CMOS process show that, under the same static power consumption and supply voltage level of 1.2-V, the proposed circuit exhibits better linearity.
Keywords :
CMOS analogue integrated circuits; MOSFET; analogue multipliers; low-power electronics; CMOS four-quadrant analog multiplier; CMOS process; MOSFET; compact four-quadrant analog multiplier circuit; low quiescent power consumption; low-voltage operation; static power consumption; supply voltage; CMOS process; Circuit simulation; Circuit topology; Energy consumption; Frequency; Joining processes; Linearity; MOSFETs; Power supplies; Voltage;
Conference_Titel :
Circuit Theory and Design, 2007. ECCTD 2007. 18th European Conference on
Conference_Location :
Seville
Print_ISBN :
978-1-4244-1341-6
Electronic_ISBN :
978-1-4244-1342-3
DOI :
10.1109/ECCTD.2007.4529705
