DocumentCode
1569659
Title
Probabilistic theory for semi-blind oversampling burst-mode clock and data recovery circuits
Author
Shastri, Bhavin J. ; Plant, David V.
Author_Institution
Dept. of Electr. & Comput. Eng., McGill Univ., Montreal, QC, Canada
fYear
2010
Firstpage
161
Lastpage
164
Abstract
We develop a unified probabilistic theory for phase-locked clock and data recovery circuits (CDRs), CDRs based on N×-oversampling techniques in either the time- or space domain, and burst-mode CDRs built from oversampling CDRs. This theory quantitatively explains the performance of these circuits in terms of the bit error rate.
Keywords
clock and data recovery circuits; clocks; error statistics; phase locked loops; time-domain analysis; bit error rate; burst-mode CDR; data recovery circuits; oversampling techniques; phase-locked clock; probabilistic theory; semiblind oversampling burst-mode clock; space domain; time-domain; Circuits; Clocks; Gaussian noise; Optical fiber networks; Optical network units; Optical noise; Optical receivers; Optical sensors; Passive optical networks; Sampling methods;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (MWSCAS), 2010 53rd IEEE International Midwest Symposium on
Conference_Location
Seattle, WA
ISSN
1548-3746
Print_ISBN
978-1-4244-7771-5
Type
conf
DOI
10.1109/MWSCAS.2010.5548587
Filename
5548587
Link To Document