Hardware efficient fixed-point VLSI architecture for 2D Kurtotic FastICA

Fixed-point VLSI architecture for 2-Dimensional Kurtotic FastICA with reduced and optimized arithmetic units, is proposed. This reduction is achieved through the removal of the dividers for eigenvector computation and replacing the dividers in the Whitening block of the architecture by multipliers. In addition, the number of multipliers required in the Whitening block is further reduced by exploiting datapath symmetry present in that block. We have addressed also the numerical error issue associated with the finite wordlength representation of fixed-point arithmetic and proposed an efficient approach in dealing with such error. The proposed architecture occupies 3.55 mm silicon area and consumes 27.1 muW power at 1.2 V @ 1 MHz using 0.13 mum standard cell CMOS technology.