3D multi-layer vision architecture for surveillance and reconnaissance applications

Author

Földesy, Peter ; Carmona-Galan, Ricardo ; Zarándy, Ákos ; Rekeczky, Csaba ; Vázquez, Angel Rodríguez ; Roska, Tamás

Author_Institution

Comput. & Autom. Res. Inst., Hungarian Acad. of Sciencies (MTA-SZTAKI), Budapest, Hungary

fYear

2009

Firstpage

185

Lastpage

188

Abstract

The architecture and the design details of a multilayer combined mixed-signal and digital sensor-processor array chip is shown. The processor layers are fabricated with 3D integration technology, and the sensor layer is integrated via bump bonding technology. The chip is constructed of a 320 x 240 sensor array layer, closely coupled with a 160 x 120 mixed-signal processor array layer, a digital frame buffer layer, and an 8 x 8 digital fovea processor array layer. The chip is designed to solve image registration and feature extraction above 1000FPS.

Keywords

computer vision; logic design; microprocessor chips; mixed analogue-digital integrated circuits; surveillance; 3D integration technology; 3D multilayer vision architecture; bump bonding technology; digital fovea processor array layer; digital frame buffer layer; digital sensor-processor array chip; feature extraction; image registration; mixed-signal processor array layer; processor layers; reconnaissance applications; sensor array layer; sensor layer; surveillance applications; Bonding; Computer architecture; Image resolution; Intelligent sensors; Reconnaissance; Sensor arrays; Signal processing; Signal resolution; Silicon; Surveillance;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuit Theory and Design, 2009. ECCTD 2009. European Conference on

Conference_Location

Antalya

Print_ISBN

978-1-4244-3896-9

Electronic_ISBN

978-1-4244-3896-9

Type

conf

DOI

10.1109/ECCTD.2009.5274944

Filename

5274944