A pixel-parallel cellular processor array in a stacked three-layer 3D silicon-on-insulator technology

This paper presents the design of a vertically-integrated image sensor/processor device, implemented in a fully stacked 3-layer three-dimensional (3D) silicon on insulator (SOI) 150nm CMOS technology. This prototype ´vision chip´ contains a 32 times 32 pixel-parallel processor array. Three silicon layers contain current-mode image sensors, current-mode analogue circuits and digital logic circuits, respectively. The two bottom layers form a mixed-mode cellular processor array, which operates in SIMD mode, and processes the image data acquired by the top-layer backside illuminated photosensor circuit. The intra-processor inter-layer communication is achieved by means of through-silicon vias, and the system is partitioned to minimise the area overhead associated with this communication. The processor comprises 4 analogue and 12 binary registers, and supports arithmetic and logic operations. Various sensor structures have been implemented to evaluate the efficiency of photo-sensing in SOI technology. The prototype circuit measures 2 mm times 2 mm, with 30 mum times 30 mum pixel pitch. The architecture and circuit design issues are presented in the paper.