Very high-speed carry computation based on mixed dynamic/transmission-gate Full Adders

In this paper, a circuit design approach to perform very fast carry computation in cascaded Full Adders is proposed. The strategy is based on the adoption of mixed dynamic and transmission-gate Full Adder topologies, as opposite to the traditional approach based on cascaded Full Adders based on the same logic style. Analysis shows that the insertion of transmission-gate Full Adders between dynamic Full Adders does not violate the timing constraints that are required by the latter ones to achieve a correct operation. To evaluate the achievable performance, the proposed approach is compared with traditional domino Full Adder chains. Post- layout simulations on a 90-nm CMOS technology show that the proposed approach outperform the domino speed performance by more than 30%, without degrading the energy efficiency and with no area penalty.