Insertion loss analysis in a photonic interconnection network for on-chip and off-chip communications

Author

Chan, Johnnie ; Biberman, Aleksandr ; Lee, Benjamin G. ; Bergman, Keren

Author_Institution

Dept. of Electr. Eng., Columbia Univ., New York, NY

fYear

2008

Firstpage

300

Lastpage

301

Abstract

An on-chip photonic interconnection network is simulated to determine statistical insertion losses for different network sizes and non-blocking switch layouts. For an 8times8 folded-torus network, we obtain an optical link loss budget of 15.5 dB.

Keywords

integrated optics; integrated optoelectronics; network-on-chip; optical communication; optical interconnections; optical losses; statistical analysis; folded-torus network; insertion loss analysis; loss 15.5 dB; networks-on-chip; nonblocking switch layouts; off-chip communications; on-chip communications; optical link loss budget; photonic interconnection network; statistical insertion losses; Bandwidth; Delay; Insertion loss; Multiprocessor interconnection networks; Network-on-a-chip; Optical interconnections; Optical losses; Optical packet switching; Optical switches; Optical waveguides;

fLanguage

English

Publisher

ieee

Conference_Titel

IEEE Lasers and Electro-Optics Society, 2008. LEOS 2008. 21st Annual Meeting of the

Conference_Location

Acapulco

Print_ISBN

978-1-4244-1931-9

Electronic_ISBN

978-1-4244-1932-6

Type

conf

DOI

10.1109/LEOS.2008.4688609

Filename

4688609

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1569823