A CMOS 3.2 GB/s serial link transceiver, using PWM and PAM scheme

In this paper, a 3.2 Gb/s serial link transceiver, in a 0.35 mum CMOS technology is presented. This serial link utilizes a new multi level pulse-width and pulse-amplitude modulation technique. By using PWM, clock is embedded in the encoded signals. Thus, in the receiver, a conventional PLL can easily extract the clock from the incoming data stream. The multilevel PAM scheme also reduces the symbol rate, as compared to a conventional 2-PAM system. In proposed architecture the minimum pulse width is equal to 4 Tb/3. Due to a larger pulse width than the conventional NRZ, with pulse width of Tb, ISI can be improved. The multiphase output of a three stage ring oscillator VCO in the PLL can be used to modulate and demodulate the signal. A new charge pump circuit is also introduced to decrease the mismatch between up and down path. The jitter of recovered clock is 13.9 ps at 800 MHz. The transmitter and receiver power consumption is 200 and 35 mW, respectively.