Title :
Circuit implementation of piecewise-affine functions based on a binary search tree
Author :
Oliveri, A. ; Oliveri, A. ; Poggi, T. ; Storace, M.
Author_Institution :
Biophys. & Electron. Eng. Dept., Univ. of Genoa, Genova, Italy
Abstract :
In this paper we introduce a digital architecture implementing piecewise-affine functions defined over domains partitioned into polytopes: the functions are linear affine over each polytope. The polytope containing the input vector is found by exploring a previously constructed binary search tree. Once the polytope is detected, the function is evaluated by addressing an affine map whose coefficients are stored in a memory. The architecture has been implemented on FPGA and experimental results for a benchmark example are shown.
Keywords :
piecewise linear techniques; trees (mathematics); FPGA; binary search tree; circuit implementation; digital architecture; piecewise-affine functions; Algorithm design and analysis; Binary search trees; Circuits; Electronic mail; Energy consumption; Field programmable gate arrays; Frequency estimation; Memory architecture; Throughput; Vectors;
Conference_Titel :
Circuit Theory and Design, 2009. ECCTD 2009. European Conference on
Conference_Location :
Antalya
Print_ISBN :
978-1-4244-3896-9
Electronic_ISBN :
978-1-4244-3896-9
DOI :
10.1109/ECCTD.2009.5274957
