Title :
An On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise
Author :
Nakamura, Yasumi ; Takamiya, Makoto ; Sakurai, Takayasu
Author_Institution :
Tokyo Univ., Tokyo
Abstract :
An on-chip noise canceller with high voltage supply lines for the nanosecond-range power supply noise is proposed. The canceller fabricated with 90-nm CMOS achieves 68% noise reduction with 2.0% power increase. Under the same noise reduction conditions, the area penalty for the canceller is 1/77 and 1/45 of those for the additional on-chip decoupling capacitors and the power supply lines respectively.
Keywords :
VLSI; capacitors; integrated circuit design; integrated circuit noise; interference suppression; low-power electronics; power supply circuits; CMOS fabrication technique; area penalty; high voltage supply lines; nanosecond-range power supply noise; noise reduction conditions; on-chip decoupling capacitors; on-chip noise canceller; size 90 nm; Capacitors; Clocks; Current supplies; Logic circuits; Noise cancellation; Noise reduction; Power supplies; Switches; Very large scale integration; Voltage;
Conference_Titel :
VLSI Circuits, 2007 IEEE Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-900784-05-5
Electronic_ISBN :
978-4-900784-05-5
DOI :
10.1109/VLSIC.2007.4342683
