Title :
0.0234mm2/1mW DCO Based Clock/Data Recovery for Gbit/s Applications
Author :
Chao, Kuan-Hua ; Wang, Ping-Ying ; Hsu, Tse-Hsiang
Author_Institution :
MediaTek Inc., Hsin-Chu
Abstract :
A digital controlled oscillator (DCO) based clock and data recovery (CDR) circuit with mixed mode loop filter is designed and fabricated. It is composed of a digital loop filter, a DCO and an analog feed-forward charge-pump to take both advantages of digital and analog design which are 1) small area and low power 2) low latency 3) insensitive to gate oxide leakage in deep submicron process 4) good PSRR (0.447%/V). The circuit is fabricated in a 90 nm CMOS process. The core area is 0.0234 mm2, and the power consumption is less than 1mW when operating at 1.5 Gbps.
Keywords :
CMOS integrated circuits; digital filters; feedforward; mixed analogue-digital integrated circuits; oscillators; synchronisation; CDR circuit; CMOS process; DCO based clock-data recovery; PSRR; analog feed-forward charge-pump; bit rate 1.5 Gbit/s; deep submicron process; digital controlled oscillator; digital loop filter; gate oxide leakage; mixed mode loop filter; size 90 nm; CMOS process; Charge pumps; Circuits; Clocks; Delay; Digital control; Digital filters; Digital-controlled oscillators; Energy consumption; Feedforward systems; Clock Data Recovery; Digital Controlled Oscillator;
Conference_Titel :
VLSI Circuits, 2007 IEEE Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-900784-05-5
Electronic_ISBN :
978-4-900784-05-5
DOI :
10.1109/VLSIC.2007.4342686
