• DocumentCode
    1570055
  • Title

    Precursor ISI Reduction in High-Speed I/O

  • Author

    Ren, Jihong ; Lee, Haechang ; Lin, Qi ; Leibowitz, Brian ; Chen, E-Hung ; Oh, Dan ; Lambrecht, Frank ; Stojanovic, Vladimir ; Yang, Chih-Kong Ken ; Zerbe, Jared

  • Author_Institution
    Rambus Inc., Los Altos
  • fYear
    2007
  • Firstpage
    134
  • Lastpage
    135
  • Abstract
    To achieve multi-Gb/s data rates over backplane channels, equalization is required to compensate for the non-idealities of the channels. In this paper, we first show that with decision-feedback equalization (DFE) handling postcursor inter-symbol interference (ISI), cancelling precursor ISI with transmitter equalization degrades rather than improves performance for most channels. This is due to the interaction between equalization adaptation and clock-data recovery (CDR), coupled with transmitter peak-power constraint. To minimize the impact of precursor ISI on the bit-error-rate (BER), we propose a new method of adapting CDR phase for maximum voltage margin.
  • Keywords
    decision feedback equalisers; error statistics; interference suppression; intersymbol interference; synchronisation; transceivers; BER; backplane channels; bit-error-rate; clock-data recovery; decision-feedback equalization; equalization adaptation; inter-symbol interference; transceiver architecture; transmitter equalization; Backplanes; Bit error rate; Clocks; Decision feedback equalizers; Degradation; Interference cancellation; Interference constraints; Intersymbol interference; Transmitters; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 2007 IEEE Symposium on
  • Conference_Location
    Kyoto
  • Print_ISBN
    978-4-900784-05-5
  • Electronic_ISBN
    978-4-900784-05-5
  • Type

    conf

  • DOI
    10.1109/VLSIC.2007.4342687
  • Filename
    4342687