Fast acquisition frequency synthesizer with n-stage novel type cycle swallowers

A novel design for a phase-locked loop (PLL) frequency synthesizer is proposed to obtain a fast acquisition time. For conventional PLL frequency synthesizer design, the smallest frequency increment is the same as the reference frequency. Thus, a low reference frequency can only be used at the expense of a longer acquisition time. However, in the proposed PLL synthesizer, by introducing n-stage novel type cycle swallowers, the smallest frequency increment and the reference frequency can be made to be independent of each other. Therefore, by using higher feedback and reference frequencies, the proposed synthesizer can attain an acquisition performance over 10³ times faster than that of the conventional PLL synthesizer and maintain the same smallest frequency increment for the output frequency. The performance of the design is illustrated by experimental results