Title :
SCGPSim: A fast SystemC simulator on GPUs
Author :
Nanjundappa, Mahesh ; Patel, Hiren D. ; Jose, Bijoy A. ; Shukla, Sandeep K.
Author_Institution :
FERMAT Lab., Virginia Tech., Blacksburg, VA, USA
Abstract :
The main objective of this paper is to speed up the simulation performance of SystemC designs at the RTL abstraction level by exploiting the high degree of parallelism afforded by today´s general purpose graphics processors (GPGPUs). Our approach parallelizes SystemC´s discrete-event simulation (DES) on GPGPUs by transforming the model of computation of DES into a model of concurrent threads that synchronize as and when necessary. Unlike the cooperative threading model employed in the SystemC reference implementation, our threading model is capable of executing in parallel on the large number of simple processing units available on GPUs. Our simulation infrastructure is called SCGPSim and it includes a source-to-source (S2S) translator to transform synthesizable SystemC models into parallelly executable programs targeting an NVIDIA GPU. The translator retains the simulation semantics of the original designs by applying semantics preserving transformations. The resulting transformed models mapped onto the massively parallel architecture of GPUs improve simulation efficiency quite substantially. Preliminary experiments with varying-sized examples such as AES, ALU, and FIR have shown simulation speed-ups ranging from 30?? to 100??. Considering that our transformations are not yet optimized, we believe that optimizing them will improve the simulation performance even further.
Keywords :
coprocessors; discrete event simulation; hardware description languages; multi-threading; parallel architectures; program interpreters; NVIDIA GPU; RTL abstraction level; SCGPSim; SystemC designs; SystemC reference implementation; SystemC simulator; concurrent threads; cooperative threading model; discrete-event simulation; general purpose graphics processors; parallel architecture; parallelly executable programs; simulation efficiency; simulation infrastructure; simulation performance; simulation semantics; source-to-source translator; synthesizable SystemC models; Computational modeling; Concurrent computing; Discrete event simulation; Finite impulse response filter; Graphics; Parallel architectures; Parallel processing; Parallel programming; Scheduling; Yarn;
Conference_Titel :
Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-5765-6
Electronic_ISBN :
978-1-4244-5767-0
DOI :
10.1109/ASPDAC.2010.5419903