Design of new CMOS current mode min and max circuits for FLC chip applications

Presented in this paper is design of the new CMOS circuits to implement Min and Max operators. This work is based on analog advantages such as low die area, high DC range and simplicity which are added to the fuzzy system advantages. For implementing this idea, new current mode circuits are proposed which based on Wilson current mirrors. We used the one of them (min circuit) in implementing inference part of the Fuzzy Logic Controller (FLC) chip to combine the antecedents (fuzzy currents) of fuzzifier circuit. The simulation results of min and max circuits with applicable in designing FLC chip (which consists of two inputs, four membership functions for each one, sixteen rules and one output which designed in an area less than 0.1 mm²) has been done in 0.35 mum CMOS standard technology using Hspice software.