Title :
A Low Jitter 1.6 GHz Multiplying DLL Utilizing a Scrambling Time-to-Digital Converter and Digital Correlation
Author :
Helal, Belal M. ; Straayer, Matthew Z. ; Wei, Gu-Yeon ; Perrott, Michael H.
Author_Institution :
Massachusetts Inst. of Technol., Cambridge
Abstract :
This paper presents a 1.6 GHz multiplying delay-locked loop (MDLL) that leverages time-to-digital conversion and a digital correlation technique to achieve low deterministic jitter while still maintaining low random jitter. A proposed time-to-digital converter consists of a ring oscillator that is gated on and off to accurately measure time and scramble the measurement´s residual error. Using a 50 MHz reference, the prototype system has measured reference spurs less than -59 dBc and an overall measured jitter of 1.41 ps.
Keywords :
UHF circuits; analogue-digital conversion; correlation methods; delay lock loops; jitter; measurement errors; multiplying circuits; reference circuits; delay offset; digital correlation technique; frequency 1.6 GHz; frequency 50 MHz; low deterministic jitter multiplying DLL; low random jitter; measurement residual error scrambling; multiplying delay-locked loop; reference spurs; ring oscillator; time-to-digital converter; Clocks; Delay; Limit-cycles; Logic; Noise shaping; Phase measurement; Phase noise; Ring oscillators; Time measurement; Timing jitter; MDLL; TDC; correlation; delay offset; deterministic jitter; noise shaping; reference spur; scrambling;
Conference_Titel :
VLSI Circuits, 2007 IEEE Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-900784-05-5
Electronic_ISBN :
978-4-900784-05-5
DOI :
10.1109/VLSIC.2007.4342700
