• DocumentCode
    1570384
  • Title

    Processor-Based Built-in Self-Optimizer for 90nm Diode-Switch PRAM

  • Author

    Sohn, Kyomin ; Kim, Hyejung ; Yoo, Jerald ; Woo, Jeong-Ho ; Lee, Seung-Jin ; Cho, Woo-Yeong ; Lim, Bo-tak ; Choi, Byung-Gil ; Kim, Chang-Sik ; Kwak, Choong-Keun ; Kim, Chang-Hyun ; Yoo, Hoi-Jun

  • Author_Institution
    KAIST, Daejeon
  • fYear
    2007
  • Firstpage
    184
  • Lastpage
    185
  • Abstract
    A PRAM includes 8 b embedded RISC to generate the optimized internal timing and voltage parameters to control the variations of the cell resistances. The PRAM blocks with small margin window of cell resistances are detected, analyzed and controlled by processor-based built-in self-optimizer (BISO). A 4 Mb test PRAM is fabricated in a 90 nm 3-metal diode-switch PRAM cell technology. Measured margin increases by up to 221%.
  • Keywords
    built-in self test; microprocessor chips; random-access storage; reduced instruction set computing; semiconductor diodes; semiconductor switches; built-in self-optimizer; cell resistance; diode-switch PRAM cell technology; embedded RISC; margin window; processor-based BISO; size 90 nm; Diodes; Logic; Microcontrollers; Phase change random access memory; Random access memory; Reduced instruction set computing; Testing; Throughput; Timing; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 2007 IEEE Symposium on
  • Conference_Location
    Kyoto
  • Print_ISBN
    978-4-900784-05-5
  • Electronic_ISBN
    978-4-900784-05-5
  • Type

    conf

  • DOI
    10.1109/VLSIC.2007.4342707
  • Filename
    4342707
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1570384