Title :
Time Discrete Voltage Sensing and Iterative Programming Control for a 4F2 Multilevel CBRAM
Author :
Schrögmeier, P. ; Angerbauer, M. ; Dietrich, S. ; Ivanov, Maxim ; Honigschmid, H. ; Liaw, Chang-Ming ; Markert, M. ; Symanczyk, R. ; Altimime, L. ; Bournat, S. ; Müller, G.
Author_Institution :
Qimonda AG, Neubiberg
Abstract :
Multilevel read/write circuits developed for a 90 nm, 4F2, 1T1CBJ (1-transistor/1-conductive bridging junction) 4Mb CBRAM core are described for the first time. The design uses an on-pitch time-discrete voltage sensing scheme and employs a bitline (BL) charge balancing reference as well as a self-timed iterative program concept. Random read cycle times ap0.7 mus and random write cycle times ap1.35 mus are achieved.
Keywords :
integrated circuit design; memory architecture; power aware computing; random-access storage; 4F2 multilevel CBRAM; bitline charge balancing reference; conductive bridging junction; iterative programming control; multilevel read-write circuits; self-timed iterative program concept; size 90 nm; storage capacity 4 Mbit; time discrete voltage sensing; Acceleration; Bridge circuits; Circuit stability; Circuit testing; Content addressable storage; Read only memory; TV; Voltage control; CBRAM; multilevel; voltage sensing and reference;
Conference_Titel :
VLSI Circuits, 2007 IEEE Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-900784-05-5
Electronic_ISBN :
978-4-900784-05-5
DOI :
10.1109/VLSIC.2007.4342708
