Title :
A Zeroing Cell-to-Cell Interference Page Architecture with Temporary LSB Storing Program Scheme for Sub-40nm MLC NAND Flash Memories and beyond
Author_Institution :
Samsung Electron. Co., Ltd., Hwasung
Abstract :
A new page architecture with temporary LSB storing program scheme is presented as a breakthrough solution for sub-40nm FG (floating-gate) MLC NAND flash memories and beyond. Without program speed degradation, the proposed method is able to eliminate 100% BL cell-to-cell and almost 50% WL cell-to-cell coupling interferences which are well known as a most critical scaling barrier for FG NAND flash memories.
Keywords :
NAND circuits; flash memories; interference suppression; multivalued logic circuits; paged storage; cell-to-cell coupling interference elimination; critical scaling barrier; floating-gate MLC NAND flash memories; size 40 nm; temporary LSB storing program scheme; zeroing cell-to-cell interference page architecture; Degradation; Equations; Finishing; Interference elimination; Nonvolatile memory; Research and development; Scalability; Service oriented architecture; Voltage;
Conference_Titel :
VLSI Circuits, 2007 IEEE Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-900784-05-5
Electronic_ISBN :
978-4-900784-05-5
DOI :
10.1109/VLSIC.2007.4342709
