3D integrated scalable focal-plane processor array

Author

Földesy, Péter ; Zarándy, Ákos ; Rekeczky, Csaba ; Roska, Tamás

Author_Institution

Analogic & Neural Comput. Lab., Hungarian Acad. of Sci., Budapest

fYear

2007

Firstpage

954

Lastpage

957

Abstract

The ASIC implementation of a 64times64 sized mixed-signal cellular visual microprocessor architecture with digital processors is described. Measurement results are shown. The architecture is composed of a regular photosensor readout circuit array, prepared for 3D sensor integration, an array of identical SIMD processing elements, and central program scheduler. The processing architecture supports cluster formation of differently parameterized arrays.

Keywords

focal planes; integrated optoelectronics; microprocessor chips; mixed analogue-digital integrated circuits; optical sensors; readout electronics; 3D integrated scalable focal-plane processor array; 3D sensor integration; ASIC implementation; digital processors; mixed-signal cellular visual microprocessor; photosensor readout circuit array; Application specific integrated circuits; Computer architecture; Computer interfaces; Integrated circuit interconnections; Processor scheduling; Sensor arrays; Sensor phenomena and characterization; Silicon; Space technology; Xenon;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuit Theory and Design, 2007. ECCTD 2007. 18th European Conference on

Conference_Location

Seville

Print_ISBN

978-1-4244-1341-6

Electronic_ISBN

978-1-4244-1342-3

Type

conf

DOI

10.1109/ECCTD.2007.4529756

Filename

4529756