Title :
A 14b Low-power Pipeline A/D Converter Using a Pre-charging Technique
Author :
Honda, Kazutaka ; Liu, Zheng ; Furuta, Mamoru ; Kawahito, S.
Author_Institution :
Shizuoka Univ., Shizuoka
Abstract :
A pre-charging technique to improve the settling response of pipeline stages is demonstrated in a Mbit pipeline A/D converter (ADC). The prototype ADC fabricated in a 0.25 mum CMOS process consumes 102 mW at 30 MSample/s. Measured SNDR and SFDR are 70.7 dB and 82.8 dB, respectively.
Keywords :
CMOS integrated circuits; analogue-digital conversion; convertors; low-power electronics; ADC fabrication; CMOS process; low-power pipeline A/D converter; power 102 mW; pre-charging technique; settling response; size 0.25 mum; word length 14 bit; Degradation; Ice; Pipelines; Power dissipation; Prototypes; Sampling methods; Tellurium; Transient response; Voltage; Wireless communication;
Conference_Titel :
VLSI Circuits, 2007 IEEE Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-900784-05-5
Electronic_ISBN :
978-4-900784-05-5
DOI :
10.1109/VLSIC.2007.4342712
