Title :
A 9Onm CMOS 0.28mm2 1V 12b 40MS/s ADC with 0.39pJ/Conversion-Step
Author :
Lee, Kang-Jin ; Shin, Eun-Seok ; Yang, Hee-Suk ; Kim, Ju-Hwa ; Ko, Pil-Un ; Kim, Il-Ryong ; Lee, Seung-Hoon ; Moon, Kyoung-Ho ; Kim, Jae-Whui
Author_Institution :
Samsung Electron. Co., Yongin
Abstract :
A 1V 12b 40MS/s pipelined ADC using a proposed two stage folded cascaded opamp for low voltage and a proposed frequency compensation technique for fast settling achieves a FOM of 0.39pJ/conversion-step. The prototype ADC implemented in a 90nm digital CMOS process with an active die area of 0.28mm2 consumes 16mW from a 1V power supply. It shows 62dB SNDR and 73dB SFDR for a 5 MHz input at a 40MHz sampling clock.
Keywords :
CMOS digital integrated circuits; Fourier transform spectra; analogue-digital conversion; integrated circuit design; operational amplifiers; CMOS pipelined ADC; FFT spectrum; digital CMOS process; energy 0.39 pJ; frequency 40 MHz; frequency 5 MHz; frequency compensation technique; multiplying-DAC; power 16 mW; sampling clock; size 90 nm; two stage folded cascaded opamp; voltage 1 V; CMOS process; Circuits; Dynamic range; Low voltage; Moon; Portable media players; Prototypes; Tellurium; Nano Scale and Low Voltage; Pipeline ADC;
Conference_Titel :
VLSI Circuits, 2007 IEEE Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-900784-05-5
Electronic_ISBN :
978-4-900784-05-5
DOI :
10.1109/VLSIC.2007.4342713
