Title :
Topology selection of FPGA look-up tables for low-leakage operation
Author :
Nair, Pradeep S. ; Koppa, Santosh ; John, Eugene B. ; Kudithipudi, Dhireesha
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Texas at San Antonio, San Antonio, TX, USA
Abstract :
Modern field-programmable gate arrays (FPGAs) are increasingly becoming prone to leakage power dissipation, which can be attributed to their flexibility and increasing densities. One of the most important types of elements that are used throughout the FPGA fabric are the NMOS pass-transistor based multiplexers, which play a prominent role in both the logic and routing blocks. In this paper, we undertake a comparative study of various FPGA-LUT topologies that are based on different constituent multiplexers from a leakage power dissipation perspective, for a 45 nm CMOS process. We found that a LUT constructed with two 8:1 decoded multiplexers or with three 4:1 multiplexers has lesser amount of leakage when compared to other topologies.
Keywords :
CMOS logic circuits; MOSFET; field programmable gate arrays; multiplexing equipment; network topology; table lookup; CMOS process; FPGA look-up table; NMOS pass-transistor based multiplexer; field-programmable gate array; leakage power dissipation; low-leakage operation; size 45 nm; topology selection; CMOS logic circuits; CMOS process; Fabrics; Field programmable gate arrays; MOS devices; Multiplexing; Power dissipation; Routing; Table lookup; Topology; Field-programmable gate arrays (FPGAs); leakage; low-power; multiplexers;
Conference_Titel :
Circuit Theory and Design, 2009. ECCTD 2009. European Conference on
Conference_Location :
Antalya
Print_ISBN :
978-1-4244-3896-9
Electronic_ISBN :
978-1-4244-3896-9
DOI :
10.1109/ECCTD.2009.5274987
