Impact of clock slope on energy/delay of pulsed flip-flops and optimum clock domain design

In this paper, the influence of the clock slope (i.e., rise/fall time) on the performance and the energy dissipation of Pulsed flip-flop (FF) topologies is investigated. Results show that the adoption of a greater clock slope leads to a slight flip-flop energy increase, as well as to a negligible speed penalty. This insensitivity of Pulsed FF performance on the clock slope is shown to be a significant advantage that permits to relax (i.e., increase) the clock slope requirement at a given FF performance. In turn, this allows for downsizing the buffers of the local clock network, thereby reducing the overall energy dissipation within a clock domain. Detailed analysis shows that an optimum clock slope exists that minimizes the energy associated with the clock network within a clock domain. This optimization is shown to bring significant energy savings, which can be close to 50 % for a FF speed degradation of only a few percentage points. Extensive post-layout simulations are performed on a 65-nm CMOS technology to validate the theoretical results.