Design of a Multi-Core SoC with Configurable Heterogeneous 9 CPUs and 2 Matrix Processors

Author

Nakajima, Masami ; Kondo, Hiroyuki ; Okumura, Naoto ; Masui, Norio ; Takata, Yukari ; Nasu, Takashi ; Takata, Hirokazu ; Higuchi, Takashi ; Sakugawa, Mamoru ; Yoneda, Hirokazu ; Fujiwara, Hayato ; Ishida, Kazuya ; Ishimi, Koichi ; Kaneko, Satoshi ; Itoh,

Author_Institution

Renesas Technol. Corp., Itami

fYear

2007

Firstpage

14

Lastpage

15

Abstract

A multi-core SoC for multi-application (recognition, inference, measurement, control, and security) is developed. The configurable heterogeneous architecture with 9 CPUs and 2 matrix processors reduced 45% power consumption. The performance-oriented multi-bank matrix processor with 2-read-1-write calculation and background I/O operation is adopted. The 1 GHz CPU is realized by the delay management network applied for any kinds of applications and process technologies.

Keywords

computer architecture; delay circuits; logic design; microprocessor chips; system-on-chip; 2-read-1-write calculation; CPU; background I/O operation; configurable heterogeneous architecture; delay management network; frequency 1 GHz; multicore SoC design; performance-oriented multibank matrix processor; Clocks; Energy consumption; Frequency; Phase measurement; Radio control; Semiconductor device measurement; Size control; Symmetric matrices; Thermal management; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2007 IEEE Symposium on

Conference_Location

Kyoto

Print_ISBN

978-4-900784-05-5

Electronic_ISBN

978-4-900784-05-5

Type

conf

DOI

10.1109/VLSIC.2007.4342717

Filename

4342717