DocumentCode
1570625
Title
A 19-mode 8.29mm2 52-mW LDPC Decoder Chipp for IEEE 802.16e System
Author
Shih, Xin-Yu ; Zhan, Cheng-Zhou ; Lin, Cheng-Hung ; Wu, An-Yeu
Author_Institution
Nat. Taiwan Univ., Taipei
fYear
2007
Firstpage
16
Lastpage
17
Abstract
This paper presents a LDPC decoder chip supporting all 19 modes in IEEE 802.16e system. An efficient design strategy is proposed to reduce 31.25% decoding latency, and enhance hardware utilization ratio from 50% to 75%. Besides, we propose an early termination scheme that can dynamically adjust the number of iterations. The multi-mode chip can be maximally measured at 83.3 MHz with only 52 mW power consumption. The core area is 4.45 mm2 and the die area is 8.29 mm2.
Keywords
WiMax; broadband networks; decoding; integrated circuit design; iterative decoding; low-power electronics; parity check codes; 19-mode LDPC decoder chip; IC design strategy; IEEE 802.16e system; decoding latency reduction; frequency 83.3 MHz; hardware utilization ratio enhancement; iterations; multimode chip; power 52 mW; power consumption; termination scheme; Block codes; CMOS technology; Communication channels; Delay; Distributed computing; Hardware; Iterative decoding; Parity check codes; Reconfigurable architectures; Routing; IEEE 802.16e; LDPC; early termination;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2007 IEEE Symposium on
Conference_Location
Kyoto
Print_ISBN
978-4-900784-05-5
Electronic_ISBN
978-4-900784-05-5
Type
conf
DOI
10.1109/VLSIC.2007.4342718
Filename
4342718
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