DocumentCode
1570632
Title
Research and implementation of Gigabit Ethernet full line rate
Author
Duan, Meixia ; Han, Hongling
Author_Institution
Dept. of Inf. Eng., North China Univ. of Water Resources & Electr. Power, Zhengzhou, China
Volume
1
fYear
2011
Firstpage
736
Lastpage
738
Abstract
The current router or switch products provide Gigabit Ethernet interfaces. High-speed FPGA design technology is used to achieve full line rate Gigabit Ethernet testing, this paper describes the software and hardware design of technical solutions, and FPGA design of the main idea of the internal procedures is described in more detail. Test results show that the design ideas and solutions can meet the requirement on the full line rate Gigabit Ethernet performance testing.
Keywords
field programmable gate arrays; hardware-software codesign; local area networks; logic design; Gigabit Ethernet interfaces; full line rate Gigabit Ethernet performance testing; high-speed FPGA design technology; router; software-hardware design; switch products; Clocks; IP networks; Semiconductor device measurement; Size measurement; Testing; cross sub-networks; full line rate; throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Cross Strait Quad-Regional Radio Science and Wireless Technology Conference (CSQRWC), 2011
Conference_Location
Harbin
Print_ISBN
978-1-4244-9792-8
Type
conf
DOI
10.1109/CSQRWC.2011.6037058
Filename
6037058
Link To Document