Author :
Ito, Masaki ; Todaka, Takashi ; Tsunoda, Takanobu ; Tanaka, Hiroya ; Kodama, Tomoyuki ; Shikano, Hiroaki ; Onouchi, Masafumi ; Uchiyama, Kunio ; Odaka, Toshihiko ; Kamei, Tatsuya ; Nagahama, Ei ; Kusaoke, Manabu ; Nitta, Yusuke ; Wada, Yasutaka ; Kimura,
Abstract :
A heterogeneous multiprocessor on a chip has been designed and implemented. It consists of 2 CPUs and 2 DRPs (Dynamic Reconfigurable Processors). The design of DRP was intended to achieve high-performance in a small area to be integrated on a SoC for embedded systems. Memory architecture of CPUs and DRPs were unified to improve programming and compiling efficiency. 54times AAC-LC stereo encoding has been enabled with 2 DRPs at 300 MHz and 2 CPUs at 600 MHz.
Keywords :
embedded systems; encoding; logic design; microprocessor chips; reconfigurable architectures; system-on-chip; AAC-LC stereo encoding; CPU memory architecture; DRP design; SoC; dynamic reconfigurable processors; embedded systems; frequency 300 MHz; frequency 600 MHz; heterogeneous multiprocessor on chip; Computer architecture; Embedded system; Encoding; Engines; Frequency; Indium tin oxide; Laboratories; Memory architecture; Switches; System-on-a-chip; SoC; dynamic reconfigurable processor; embedded system and AAC; multiprocessor;
