Homogenous Dual-Processor core with Shared L1 Cache for Mobile Multimedia SoC

We propose a novel dual-processor core which adopts a shared L1 cache with active way scheme. In this scheme, each WAY of cache is owned by specific processor and replace operation is only happened to its own WAYs. This architecture only requires dual port TAG, and no dual port DATA memory to realize simultaneous access from both processors, and can guarantee no cache thrashing and no snoop overhead. And also by sharing cache memory and cache controller, power dissipation is 23% smaller in case of heavy load and area is 29 % smaller than dual processor core with snoop cache.