Development of side-channel attack standard evaluation environment

Author

Katashita, Toshihiro ; Satoh, Akashi ; Sugawara, Takeshi ; Homma, Naofumi ; Aoki, Takafumi

Author_Institution

Res. Center for Inf. Security, Nat. Inst. of Adv. Ind. Sci. & Technol., Tokyo, Japan

fYear

2009

Firstpage

403

Lastpage

408

Abstract

An experimental FPGA board SASEBO-GII has been developed as a standard platform for advanced research on side-channel attacks and countermeasures. The board is equipped with a new FPGA device, Virtex-5 LX30/50, which provides large logic capacity and dynamic partial reconfiguration. Configuration data can be transferred from a host PC to the FPGA through a USB interface without using a JTAG cable. The USB port can also supply power for operation to the board. Even with these additional functionalities, the size of SASEBO-GII is 1/3 that of the previous board, SASEBO-G. The compactness and circuit design reduce noise that disrupts side-channel analysis. In the paper, the advantages of SASEBO-GII are demonstrated through various AES implementations and CPA experiments.

Keywords

cryptography; field programmable gate arrays; standards; FPGA device; SASEBO-GII; Virtex-5 LX30/50; side-channel attack standard evaluation environment; Circuit noise; Circuit synthesis; Communication cables; Field programmable gate arrays; Logic devices; Noise reduction; Power supplies; Reconfigurable logic; Standards development; Universal Serial Bus;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuit Theory and Design, 2009. ECCTD 2009. European Conference on

Conference_Location

Antalya

Print_ISBN

978-1-4244-3896-9

Electronic_ISBN

978-1-4244-3896-9

Type

conf

DOI

10.1109/ECCTD.2009.5275001

Filename

5275001