DocumentCode :
1570819
Title :
Multiphase-Output Level Shift System used in Multiphase PLL for Low Power Application
Author :
Matsumoto, Akinori ; Sakiyama, Shiro ; Tokunaga, Yusuke ; Morie, Takashi ; Dosho, Shiro
Author_Institution :
Matsushita Electr. Ind. Co., Ltd., Osaka
fYear :
2007
Firstpage :
228
Lastpage :
229
Abstract :
Low power design is essential for mobile application. For a PLL with multiphase outputs, level shifter (LS), which converts oscillator-output-level to that of power supply, consumes much power; hence, we have devised a new architecture called a multiphase-output level shift system (M-LSs) which has only three transistors in each LS and cuts off short current perfectly. Moreover, we have connected between the adjacent phases of M-LSs with a resistor to improve phase accuracy. The two key techniques mentioned above make power consumption 1/15 of the conventional LS. The PLL consumes about 1 mA at 123 MHz and accomplishes 63-phase accuracy of 0.5LSB.
Keywords :
oscillators; phase locked loops; transistors; multiphase PLL; multiphase-output level shift system; transistors; Clocks; Degradation; Electricity supply industry; Energy consumption; MOS devices; Phase locked loops; Power generation; Power measurement; Power supplies; Resistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Circuits, 2007 IEEE Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-900784-05-5
Electronic_ISBN :
978-4-900784-05-5
Type :
conf
DOI :
10.1109/VLSIC.2007.4342729
Filename :
4342729
Link To Document :
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