Title :
A PVT Tolerant PLL with On-Chip Loop-Transfer-Function Calibration Circuit
Author :
Kondou, Masafumi ; Mori, Toshihiko
Author_Institution :
Fujitsu Lab. Ltd., Kawasaki
Abstract :
A PVT tolerant PLL architecture which uses two on-chip digital calibration circuits to maintain loop transfer function is presented. Test chips with 9 conditions, MOSes, resistors and capacitors, were fabricated in a 90 nm CMOS technology. Experimental results show that the phase noise remains + 2dBc/Hz within 10 MHz offset under any PVT condition.
Keywords :
CMOS digital integrated circuits; calibration; phase locked loops; phase noise; CMOS technology; MOSes; PVT tolerant PLL architecture; PVT variation; capacitors; on-chip digital calibration circuits; on-chip loop-transfer-function; phase noise; resistors; CMOS technology; Calibration; Capacitance; Charge pumps; Circuits; Phase locked loops; Phase noise; Poles and zeros; Transfer functions; Voltage-controlled oscillators; PLL; loop-transfer-function and calibration;
Conference_Titel :
VLSI Circuits, 2007 IEEE Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-900784-05-5
Electronic_ISBN :
978-4-900784-05-5
DOI :
10.1109/VLSIC.2007.4342731
