Title :
Avoiding false paths caused by resource binding in RTL delay analysis
Author :
Nourani, Mehrdad ; Papachristou, Christos
Author_Institution :
Dept. of Electr. Eng. & Comput. Eng., Tehran Univ., Iran
Abstract :
In this paper, we present an accurate delay estimation algorithm at the register transfer level. We introduce “resource binding” as on important source of false paths in a register transfer level structure. The existence and creation of such paths and their effect in delay analysis are discussed. We also introduce the Propagation Delay Graph (PDG), whose traversal, for delay analysis, is equivalent to the traversal of sensitizable paths in the datapath
Keywords :
cellular arrays; delays; high level synthesis; logic CAD; RTL delay analysis; cell-based designs; delay estimation algorithm; false paths; high level synthesis; propagation delay graph; register transfer level; resource binding; sensitizable paths; Circuit synthesis; Clocks; Delay estimation; Design engineering; High level synthesis; Logic design; Propagation delay; Registers; Silicon compiler; Wire;
Conference_Titel :
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location :
Atlanta, GA
Print_ISBN :
0-7803-3073-0
DOI :
10.1109/ISCAS.1996.542000
