Title :
Timing optimization algorithm for design of high performance VLSI systems
Author :
Lee, Taegyu ; Hoon Chung
Author_Institution :
Sch. of Comput., SoongSil Univ., Seoul, South Korea
Abstract :
In designing VLSI systems, need for high performance and reliability is becoming an important issue. This paper provides an algorithm which can achieve high performance and reliability by optimizing delays of components to satisfy the timing constraints. A unified algorithm which executes optimization by adjusting the path delays of circuits in a more efficient way within reasonable computer time and memory requirements. Experimental result shows the efficiency of the proposed algorithm
Keywords :
VLSI; circuit CAD; circuit optimisation; delays; flip-flops; integrated circuit design; integrated circuit reliability; logic CAD; sequential circuits; timing; IC design; algorithm efficiency; computer time; flip flops; high performance VLSI systems; path delays; reliability; timing constraints; timing optimization algorithm; Algorithm design and analysis; Clocks; Constraint optimization; Design optimization; Frequency; High performance computing; Integrated circuit interconnections; Propagation delay; Timing; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location :
Atlanta, GA
Print_ISBN :
0-7803-3073-0
DOI :
10.1109/ISCAS.1996.542002
