Title :
A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues
Author :
Ishikura, S. ; Kurumada, M. ; Terano, T. ; Yamagami, Y. ; Kotani, N. ; Satomi, K. ; Nii, K. ; Yabuuchi, M. ; Tsukamoto, Y. ; Ohbayashi, S. ; Oashi, T. ; Makino, H. ; Shinohara, H. ; Akamatsu, H.
Author_Institution :
Matsushita Electr. Ind. Co. Ltd., Kyoto
Abstract :
We propose a new 2port (2P) SRAM with an 8T single-bit-line (SBL) memory cell for 45 nm SOCs. Access time tends to be slower as the device size is scaled down because of the random threshold-voltage variations. The Divided read Bit line scheme with Shared local Amplifier (DBSA) realizes fast access time without increasing area penalty. We also show an additional important issue of a simultaneous Read and Write (R/W) access at the same row by using DBSA with the 8 T-SBL memory cell. A rise of the storage node voltage causes the misreading. The Read End detecting Replica circuit (RER) and the Local read bit line with Dummy Capacitance (LDC) are introduced to solve this issue. A 128 BLtimes512WL 64Kb 2P-SRAM macro which cell size is 0.597mum2 using these schemes was fabricated by 45 nm LSTP CMOS process.
Keywords :
CMOS memory circuits; SRAM chips; system-on-chip; LSTP CMOS process; SOC; SRAM; divided read bit line scheme; dummy capacitance; hierarchical replica bitline technique; memory cell; random threshold-voltage variations; read end detecting replica circuit; shared local amplifier; simultaneous R/W access issues; size 45 nm; CMOS process; CMOS technology; Capacitance; Circuits; Degradation; Leakage current; MOSFETs; Random access memory; Timing; Voltage;
Conference_Titel :
VLSI Circuits, 2007 IEEE Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-900784-05-5
Electronic_ISBN :
978-4-900784-05-5
DOI :
10.1109/VLSIC.2007.4342740
