Title :
A full parallel priority encoder design used in comparator
Author :
Huang, Shao-Wei ; Chang, Yen-Jen
Author_Institution :
Dept. of Comput. Sci. & Eng., Nat. Chung-Hsing Univ., Taichung, Taiwan
Abstract :
In this paper, we present an enhanced priority encoder, called full parallel priority encoder (FPPE) that can be used in the comparator circuitry. Because there is no serial NAND-type path, the performance of FPPE is better than that of the conventional priority encoder. The comparator with FPPE is implemented in UMC 90nm CMOS technology. The simulation results show that the proposed design is 40% and 12% faster than the comparator based on NAND-type priority encoder and the comparator based on parallel MSB checking comparison, respectively.
Keywords :
CMOS integrated circuits; comparators (circuits); FPPE; UMC 90nm CMOS technology; comparator circuitry; full parallel priority encoder design; serial NAND-type path; size 90 nm; CMOS digital integrated circuits; CMOS technology; Circuit simulation; Clocks; Computational modeling; Computer science; Data conversion; Design engineering; Inverters; MOSFETs; CMOS dynamic circuit; Comparator; Priority encoder;
Conference_Titel :
Circuits and Systems (MWSCAS), 2010 53rd IEEE International Midwest Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
978-1-4244-7771-5
DOI :
10.1109/MWSCAS.2010.5548664
