4.2K CMOS circuit design for digital readout of Single Electron Transistor electrometry

We present the perspective of CMOS electronics as a candidate for the readout purposes of sensing devices such as the Single Electron Transistor (SET) at very low temperature. Fully Depleted Silicon on Insulator (FD-SOI) CMOS devices are less susceptible to low temperature anomalies compared to bulk devices. The electrical characteristics of a typical SET are too small in comparison to usual current/voltage levels for MOS circuits and thus imposes new complications in circuit design. We present a digital readout scheme of the SET best suited for scalable design. The circuit is implemented with commercial 0.5μm SOI CMOS process operating at 4.2K. The simulation results show successful detection of 200pA drain current of an SET biased at 10μV with 15μs detection speed and static power dissipation less than 45μW.