DocumentCode
1571118
Title
Study on the DFG model method based on SOPC technology
Author
Shuying, Wang ; Xi, Han ; Kaishuang, Yin
Author_Institution
Coll. of Inf., Beijing Union Univ., Beijing, China
Volume
1
fYear
2011
Firstpage
835
Lastpage
838
Abstract
HW/SW (hardware/software) co-design method based on analysis and optimization of DFG (data flow graphic) model is introduced for SOPC (System on a Programmable Chip) used for digital instrument design in this paper. The method is based on the DFG model of the digital signal process algorithm and implemented with SOPC technology. The DFG model could help designer to divide the function into hardware and software respectively, therefore, the optimizing analysis at system level and circuit level of an SOPC used for portable logic analyzer shows that the DFG model is very useful for not only optimizing architecture and power consumption, but also HW/SW co-design. The DFG model method based on SOPC technology is described in detail in this paper.
Keywords
data flow graphs; digital signal processing chips; hardware-software codesign; system-on-chip; DFG model; SOPC technology; data flow graphic model; digital instrument design; digital signal process algorithm; hardware-software codesign; portable logic analyzer; system on a programmable chip; Analytical models; Computational modeling; Extraterrestrial measurements; Integrated circuit modeling; DFG Model; Evaluation; Integrated Circuit; Simulation;
fLanguage
English
Publisher
ieee
Conference_Titel
Cross Strait Quad-Regional Radio Science and Wireless Technology Conference (CSQRWC), 2011
Conference_Location
Harbin
Print_ISBN
978-1-4244-9792-8
Type
conf
DOI
10.1109/CSQRWC.2011.6037080
Filename
6037080
Link To Document