PECS: a peak current and power simulator for CMOS combinational circuits

Electromigration of metal wires and excessive heat dissipation are two common reliability problems facing IC designers today. Techniques for fast estimation of peak supply current and power dissipation in ICs to ensure proper design and long-term reliable operation are of great interest. However, finding such peak quantities in VLSI combinational circuits has always been a difficult problem due to the exponential dependence on the input vectors applied to the given circuit. Static CMOS combinational circuits complicate the problem further because such worst-case quantities depend on the application of two successive input-vector patterns. In this paper, we present a simulator that transforms the switching activity in a given CMOS combinational circuit into a set of weighted Boolean clauses in terms of the two-vector sequence. We develop transformational rules that account for differing arrival times of the input signals, gate sizes, load capacitances, and signal glitching phenomena in a given circuit. Satisfying a maximum number of the Boolean clauses, weighted appropriately by the node capacitances and strengths of transistors driving the nodes, yields the desired sequence of two input vectors. PEGS is developed to formulate the switching activity, find the worst-case input vector pattern, and calculate the peak supply current waveform as well as power dissipation from circuit netlists. Experimental results show, on the average, no more than 10% deviation from those of SPICE and a significant speedup of our simulator over SPICE