Clocked semi-floating-gate ultra low-voltage current multiplier

In this paper we present a ultra low voltage current mode multiplier. The current multiplier is based on a clocked semi floating gate design strategy used for ultra low voltage digital and analog design. By imposing offsets to semi-floating-gate nodes the current level may be increased while maintaining a very low supply voltage. The offset voltages are used to shift the effective threshold voltage of the evaluating transistors. A current multiplier able to operate at supply voltages below 200 mV is presented and simulated data are provided. The simulated data presented are obtained using the Spectre simulator provided by Cadence and valid for a 90 nm CMOS process.