Systolic-array architecture for 2D IIR Wideband dual-beam space-time plane-wave filters

A spatio-temporal 2D IIR broadband plane-wave filter having 2 user-selectable passbands is proposed using the concept of 2D network resonance. The plane-wave filter is capable of the highly-selective directional enhancement of 2 far-field plane-waves in the presence of undesired waves at different directions of arrival. A massively-parallel systolic-array processor architecture is proposed for the real-time VLSI implementation of the filter. The architecture is designed, simulated, and implemented as a prototype clocked at 50 MHz, using a Xilinx Virtex-4 Sx35-10ff668 FPGA device. The proposed systolic-array delivers a real-time throughput of one-frame-per-clock-cycle (OPFCC) which implies 50 million linear frames per second. The design is simulated (for a 32 element array) and tested on-chip (for an 18-element array) using 2D impulse- and frequency-responses, and using multi-directional broadband plane-wave test sequences.