Title :
XOR evaluation for 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplier
Author :
Anuar, N. ; Takahashi, Y. ; Sekine, Taku
Author_Institution :
Grad. Sch. of Eng., Gifu Univ., Gifu, Japan
Abstract :
This paper evaluates four designs of XOR employing our previously presented two-phase clocked adiabatic static CMOS logic (2PASCL) circuit techniques. 2PASCL XOR, which demonstrates the lowest power dissipation, is used for the 4 × 4-bit array 2PASCL multiplier. From our simulation results, at transition frequencies of 1 to 100 MHz, the 4 × 4-bit array 2PASCL multiplier shows a maximum of 55% reduction in power dissipation to that of a static CMOS.
Keywords :
CMOS logic circuits; logic circuits; multiplying circuits; 2PASCL XOR; 2PASCL circuit techniques; 2PASCL multiplier; XOR evaluation; frequency 1 MHz to 100 MHz; power dissipation; transition frequency; two-phase clocked adiabatic static CMOS logic circuit techniques; two-phase clocked adiabatic static CMOS logic multiplier; CMOS logic circuits; Circuit simulation; Clocks; Design engineering; Diodes; Energy dissipation; Frequency; Logic arrays; Logic design; Power dissipation;
Conference_Titel :
Circuits and Systems (MWSCAS), 2010 53rd IEEE International Midwest Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
978-1-4244-7771-5
DOI :
10.1109/MWSCAS.2010.5548681
