DocumentCode :
1571373
Title :
RF2: A 1GHz FIR Filter with Distributed Resonant Clock Generator
Author :
Sathe, Visvesh S. ; Kao, Jerry C. ; Papaefthymiou, Marlos C.
Author_Institution :
Michigan Univ., Ann Arbor
fYear :
2007
Firstpage :
44
Lastpage :
45
Abstract :
In this paper we present the design and experimental validation of RF2, a 1 GHz, two-phase resonant-clocked FIR filter test-chip with a distributed resonant clock generator and an on-chip inductor. RF2 is fabricated in a 0.13 mum CMOS process and dissipates 124mW at resonance, with clock power accounting for only 16% of overall power. Implemented using a fully ASIC design flow, RF2 achieves 84% clock-power efficiency over CV2f, the highest for any fully-integrated resonant-clocked chip. Resonating at 1.01 GHz, RF2 reports the highest operating frequency for a resonant-clocked datapath to date.
Keywords :
CMOS integrated circuits; FIR filters; clocks; inductors; CMOS process; FIR filter; RF2; distributed resonant clock generator; frequency 1 GHz; fully ASIC design; fully-integrated resonant-clocked chip; on-chip inductor; power 124 mW; size 0.13 mum; Clocks; Degradation; Delay; Finite impulse response filter; Flip-flops; Inductors; Pipelines; Power dissipation; Resonance; Robustness;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Circuits, 2007 IEEE Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-900784-05-5
Electronic_ISBN :
978-4-900784-05-5
Type :
conf
DOI :
10.1109/VLSIC.2007.4342759
Filename :
4342759
Link To Document :
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