A 6.5GHz 54mW 64-bit Parity-Checking Adder for 65nm Fault-Tolerant Microprocessor Execution Cores

Author

Mathew, Sanu ; Anders, Mark ; Krishnamurthy, Ram ; Borkar, Shekhar

Author_Institution

Intel Corp., Hillsboro

fYear

2007

Firstpage

46

Lastpage

47

Abstract

This paper describes a parity-checking fault-tolerant adder designed for 6.5 GHz operation with total power consumption of 54 mW, targeted for 65 nm 64-bit microprocessor execution cores. The adder is fully self-checking and guarantees 100% coverage of single-faults (including multi-bit output errors originating from single-faults) on any sequential/combinational node in the design. The sparse-tree design enables partial pre-computation of the critical carry-parities, resulting in 33% reduction in parity-computation delay overhead with a low 6% area overhead for fault-detection.

Keywords

CMOS logic circuits; adders; fault tolerance; field effect MMIC; integrated circuit design; integrated circuit testing; microprocessor chips; 64-bit parity-checking adder; combinational node; critical carry-parities; fault-detection; fault-tolerant microprocessor execution cores; frequency 6.5 GHz; multibit output errors; parity-computation delay reduction; power 54 mW; power consumption; sequential node; size 65 nm; sparse-tree design; word length 64 bit; Adders; Circuit faults; Concurrent computing; Debugging; Delay; Fault detection; Fault tolerance; Logic; Microprocessors; Signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2007 IEEE Symposium on

Conference_Location

Kyoto

Print_ISBN

978-4-900784-05-5

Electronic_ISBN

978-4-900784-05-5

Type

conf

DOI

10.1109/VLSIC.2007.4342760

Filename

4342760