DocumentCode :
1571472
Title :
Hardware/software co-simulator for ASIC DSP chips
Author :
Takanishi, Yukiko ; Mori, Koichi ; Nishitani, Takao ; Nakamura, Yuichi
Author_Institution :
Fac. of Syst. Design, Tokyo Metropolitan Univ., Asahigaoka, Japan
fYear :
2010
Firstpage :
809
Lastpage :
812
Abstract :
A hardware/software co-simulator has been developed for a video processing SOC. The simulator is composed of a PC and a FPGA board. The simulator realizes seamless connection between software on a PC and hardware circuits in a FPGA chip. Therefore, partial VLSI design is possible within the software. As modification on both software system and FPGA circuits are easy and as the simulation speed is about the same to that of system program in a high level language, simultaneous optimization of system architecture and LSI design becomes possible. The effective use of the simulator is shown by the partial implementation of an image enhancement system as an example.
Keywords :
digital signal processing chips; field programmable gate arrays; hardware-software codesign; system-on-chip; ASIC DSP chips; FPGA board; LSI design; digital signal processing; field programmable gate array; hardware-software cosimulator; image enhancement; system-on-chips; video processing SOC; Application specific integrated circuits; Circuit simulation; Computer architecture; Design optimization; Digital signal processing chips; Field programmable gate arrays; Hardware; High level languages; Software systems; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (MWSCAS), 2010 53rd IEEE International Midwest Symposium on
Conference_Location :
Seattle, WA
ISSN :
1548-3746
Print_ISBN :
978-1-4244-7771-5
Type :
conf
DOI :
10.1109/MWSCAS.2010.5548687
Filename :
5548687
Link To Document :
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