DocumentCode
1571497
Title
A 1.35 GS/s, 10b, 175 mW time-interleaved AD converter in 0.13 μm CMOS
Author
Louwsma, Simon M. ; van Tuijl, E.J.M. ; Vertregt, Maarten ; Nauta, Brami
Author_Institution
Twente Univ., Eindhoven
fYear
2007
Firstpage
62
Lastpage
63
Abstract
A time-interleaved ADC is presented with 16 channels, each consisting of two successive approximation (SA) ADCs in a pipeline configuration. Three techniques are presented to increase the speed of an SA-ADC. Single channel performance is 6.9 ENOB at an input frequency of 4 GHz. Multi-channel performance is 7.7 ENOB at 1.35 GS/s with an ERBW of 1 GHz and a FoM of 0.6 pJ/conversion-step.
Keywords
CMOS integrated circuits; analogue-digital conversion; CMOS process; frequency 1 GHz; frequency 4 GHz; multichannel performance; pipeline configuration; power 175 mW; single channel performance; size 0.13 mum; storage capacity 10 bit; successive approximation ADC; time-interleaved A/D converter; Analog-digital conversion; Clocks; Frequency; Interleaved codes; Logic; Pipeline processing; Satellite broadcasting; Signal design; Signal resolution; Switches; ADC; SA-ADC; SAR; T/H; time-interleaved;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2007 IEEE Symposium on
Conference_Location
Kyoto
Print_ISBN
978-4-900784-04-8
Electronic_ISBN
978-4-900784-05-5
Type
conf
DOI
10.1109/VLSIC.2007.4342766
Filename
4342766
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